Static Timing Analysis of Multibit Flipflop based LFSR
Author:
Affiliation:
1. R V College of Engineering,Dept. of Electronics and Communication Engineering,Bangalore,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10026329/10026357/10026403.pdf?arnumber=10026403
Reference12 articles.
1. Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization
2. Analysis of multi-bit flip flop low power methodology to reduce area and power in physical synthesis and clock tree synthesis in 90nm CMOS technology
3. A 40nm Critical Path Monitor for the Detection of Setup and Hold Time Violations
4. Multi-bit flip-flop usage impact on physical synthesis
5. Statistical static timing analysis: A survey
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