A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic-Reference-Cited by-同舟云学术

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A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic

Published:2008-05 Issue:5 Volume:16 Page:594-598
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Chua-Chin Wang ,Chi-Chun Huang ,Ching-Li Lee ,Tsai-Wen Cheng

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/4490005/04469921.pdf?arnumber=4469921

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-Speed and Energy-Efficient Carry Look-Ahead Adder;Journal of Low Power Electronics and Applications;2022-08-10

2. Design of Arithmetic Logic Unit using Pseudo Dynamic Buffer based Domino Logic;Journal of Physics: Conference Series;2020-12-01

3. Monotype Organic Dual Threshold Voltage Using Different OTFT Geometries;Crystals;2019-06-28

4. Single Event Resilient Dynamic Logic Designs;Journal of Electronic Testing;2014-11-27

5. Design of low-power modern radar SoC based on ASIX;Tsinghua Science and Technology;2014-04

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