Single Event Resilient Dynamic Logic Designs-Reference-Cited by-同舟云学术

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Single Event Resilient Dynamic Logic Designs

Published:2014-11-27 Issue:6 Volume:30 Page:751-761
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Wang H.-B.,Li M.-L.,Chen L.,Liu R.,Baeg S.,Wen S.-J.,Wong R.,Fung R.,Bi J.-S.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/s10836-014-5492-2.pdf

Reference20 articles.

1. Asadi G, Tahoori M (2005) An accurate ser estimation method based on propagation probability. in Proceedings Design, Automation and Test in Europe, 1: 306–307

2. Atkinson N, Witulski A, Holman W, Ahlbin J, Bhuva B, Massengill L. Layout technique for single-event transient mitigation via pulse quenching. IEEE Trans Nucl Sci. 2011;58(3):885–90.

3. Calin T, Nicolaidis M, Velazco R. Upset hardened memory design for submicronCMOS technology. IEEE Trans Nucl Sci. 1996;43(6):2874–8.

4. Chang S-C, Cheng C-H, Jone W-B, Lee S-D, Wang J-S. Charge-sharing alleviation and detection for cmos domino circuits. IEEE Trans Comput Aided Des Integr Circ Syst. 2001;20(2):266–80.

5. Dodd P, Massengill L. Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans Nucl Sci. 2003;50(3):583–602.

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology;Journal of Electronic Testing;2016-04-29

2. Layout-based Single Event Mitigation Techniques for Dynamic Logic Circuits;Journal of Electronic Testing;2015-12-29

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