The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx5/92/5695105/05291700.pdf?arnumber=5291700
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm;ACM Transactions on Reconfigurable Technology and Systems;2024-02-12
2. Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAs;Microprocessors and Microsystems;2022-07
3. Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm;2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2022-05-15
4. Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology;2020 30th International Conference on Field-Programmable Logic and Applications (FPL);2020-08
5. An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures;ACM Transactions on Reconfigurable Technology and Systems;2018-03-22
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