1. How much logic should go in an FPGA logic block?;Betz;IEEE Des. Test Mag.,1998
2. FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density;Betz,1999
3. Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density;Marquardt,1999
4. Speed and area tradeoffs in cluster-based FPGA architectures;Marquardt;IEEE Trans. VLSI Syst.,2000
5. Using Sparse Crossbars within LUT Clusters;Lemieux,2001