An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping-Reference-Cited by-同舟云学术

An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping

Published:2022-04 Issue:4 Volume:30 Page:379-391
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Zhang Yewei¹,Huang Kejie¹^ORCID,Xiao Rui¹^ORCID,Wang Bo²^ORCID,Xu Yanfeng³,Fan Jicong³,Shen Haibin¹^ORCID

Affiliation:

1. College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China

2. Department of Information Systems Technology and Design, Singapore University of Technology and Design, Singapore

3. China Electronics Technology Group Corporation No.58 Research Institute, Wuxi, China

Funder

Major Scientific Research Project of Zhejiang Laboratory

National Natural Science Foundation of China

National Key Research and Development Program of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/9739817/09689064.pdf?arnumber=9689064

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5. Binary convolutional neural network on RRAM

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