A Low-Power Charge-Domain Bit-Scalable Readout System for Fully-Parallel Computing-in-Memory Accelerators-Reference-Cited by-同舟云学术

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A Low-Power Charge-Domain Bit-Scalable Readout System for Fully-Parallel Computing-in-Memory Accelerators

Published:2023 Issue: Volume: Page:1-1
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Mao Wei¹^ORCID,Li Fuyi¹,Liu Jun¹,Xiao Rui²^ORCID,Huang Kejie²^ORCID,Li Yongfu³^ORCID,Yu Hao⁴,Liu Yan¹^ORCID,Han Genquan¹^ORCID

Affiliation:

1. Hangzhou Institute of Technology, Xidian University, Hangzhou, China

2. College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China

3. Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, China

4. School of Microelectronics, Southern University of Science and Technology, Shenzhen, China

Funder

National Key Research and Development Program of China

Major Program of Zhejiang Natural Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/4358609/10306248.pdf?arnumber=10306248

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