From Design to Test: A High-Speed PRBS

Author:

Zhu KehanORCID,Saxena Vishal

Funder

NSF CAREER Award

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 27-1, 20-Gb/s, 0.1-pJ/b Pseudo Random Bit Sequence Generator Using Incomplete Settling in 1.2V, 65 nm CMOS;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A Compact Low-Power 29 Gb/s Pseudo Random Quaternary Sequence Generator in 65 nm CMOS;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

3. A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks;Circuits, Systems, and Signal Processing;2023-06-19

4. An active inductor employed CML latch for high speed integrated circuits;Analog Integrated Circuits and Signal Processing;2022-08-03

5. Microring resonator-based all-optical parallel pseudo random binary sequence generator for rate multiplication;Optical and Quantum Electronics;2022-07-15

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