Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18 $\mu{\rm m}$ CMOS Analog-to-Digital Convertor

Author:

Kim Hyo-Jin,An Tai-Ji,Myung Sung-Meen,Lee Seung-Hoon

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of low power fault tolerant flash ADC for instrumentation applications;Microelectronics Journal;2020-04

2. Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC’s;IEEE Transactions on Circuits and Systems I: Regular Papers;2018-10

3. A Two-channel 10b 160 MS/s 28 nm CMOS Asynchronous Pipelined-SAR ADC with Low Channel Mismatch;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2017-10-31

4. Low-Power ${G}_{{m}}{-}C$ Filter Employing Current-Reuse Differential Difference Amplifiers;IEEE Transactions on Circuits and Systems II: Express Briefs;2017-06

5. A Power-Efficient Compact Pipelined ADC for ZigBee Receiver Applications;Journal of Circuits, Systems and Computers;2016-06-21

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