A Power-Efficient Compact Pipelined ADC for ZigBee Receiver Applications

Abstract

A pipelined analog-to-digital converter (ADC) that exhibits both power and area efficiencies is presented in this paper for ZigBee receiver applications. A combined opamp- and capacitor-sharing technique which presents a novel method to eliminate the memory effect is proposed. Fabricated in a 0.13-[Formula: see text]m CMOS process, the prototype 7-bit 16-MS/s ADC occupies 0.16[Formula: see text]mm2 active die area and achieves 41.9[Formula: see text]dB signal-to-noise-and-distortion ratio (SNDR), 52.1[Formula: see text]dB spurious-free dynamic rage (SFDR). The experimental results show that the figure of merit (FOM) is 1.12[Formula: see text]pJ/step and power dissipation is 1.82[Formula: see text]mW from a 1.2[Formula: see text]V supply.