Design of low power fault tolerant flash ADC for instrumentation applications

Author:

Prathiba G.,Santhi M.

Publisher

Elsevier BV

Subject

General Engineering

Reference28 articles.

1. Utilizing process variations for reference generation in a flash ADC ”;Timmy Sundstrom,2009

2. Ultralow-voltage high-speed flash ADC design. Strategy based on FoM-delay product;Lin,2015

3. Design and characterization of a 3-bit 24-GS/s flash ADC in 28-nm low-power digital CMOS;Gregor Tretter,2016

4. The core for high-precision stochastic smart grid meter based on low-resolution flash ADC ”;Urekar,2019

5. A low-power high-speed hybrid ADC with merged sample-and-hold and DAC functions for efficient subranging time-interleaved operation”;Alireza Zahrai,2017

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1. Design and Implementation of Low Power Flash Analog to Digital Converter;2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT);2023-04-05

2. Realization of a variable resolution modified semiflash ADC based on bit segmentation scheme;Facta universitatis - series: Electronics and Energetics;2022

3. A Novel Rail-to-Rail Input Swing Threshold-Inverter Multi-Bit Quantizer Using Interpolation Technique for Sampled-Data Circuits;Journal of Circuits, Systems and Computers;2021-09-29

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