Funder
Ministry of Science and Technology, Taiwan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
6 articles.
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1. Enhancing Static Timing Analysis Efficiency for RISC-V Processors Through Optimization Techniques;Lecture Notes on Multidisciplinary Industrial Engineering;2024
2. Physical Design Implementation of SoC Module with Performance Optimization;2023 7th International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS);2023-11-02
3. Complete Timing Model of ECSM Lookup Table for CMOS Inverter;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20
4. Accurate Timing Path Delay Learning Using Feature Enhancer with Effective Capacitance;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08
5. An Enhanced Clock Tree Synthesis Methodology for Optimizing Power in Physical Design;2022 IEEE 3rd International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2022-12-15