Accurate Timing Path Delay Learning Using Feature Enhancer with Effective Capacitance-Reference-Cited by-同舟云学术

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Accurate Timing Path Delay Learning Using Feature Enhancer with Effective Capacitance

Published:2023-05-08 Issue: Volume: Page:
ISSN:
Container-title:2023 International Symposium of Electronics Design Automation (ISEDA)
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Author:

Liu He¹,Wu Shengkun²,Tao Simin²,Xie Biwei³,Li Xingquan⁴,Li Ge¹

Affiliation:

1. School of Electronic and Computer Engineering, Peking University,Shenzhen,China

2. Peng Cheng Laboratory,Shenzhen,China

3. Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China

4. School of Mathematics and Statistics, Minnan Normal University,Zhangzhou,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10218344/10218369/10218429.pdf?arnumber=10218429

Reference16 articles.

1. ICCAD-2014 CAD contest in incremental timing-driven placement and benchmark suite: Special session paper: CAD contest

2. Accurate timing prediction at placement stage with look-ahead RC network

3. Attention enables zero approximation error;fang;ArXiv Preprint,2022

4. Deep frequency principle towards under-standing why deeper learning is faster;xu;Proceedings of the AAAI Conference on Artificial Intelligence,0

5. A timing engine inspired graph neural network model for pre-routing slack prediction

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. iPD: An Open-source intelligent Physical Design Toolchain;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

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