A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs
Author:
Affiliation:
1. Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China
Funder
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/9904512/09831161.pdf?arnumber=9831161
Reference15 articles.
1. Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS
2. A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration
3. Improved design of digital fractional-order differentiators using fractional sample delay
4. A Background Timing Skew Calibration Technique in Time-Interleaved ADCs With Second Order Compensation
5. A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS
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