Author:
Li Meng,lv fangxu,lai mingche,zheng xuqiang,Huang Heng,Qi Xingyun,zhang geng
Reference34 articles.
1. Design considerations for interleaved adcs;B Razavi;IEEE Journal of Solid-State Circuits,2013
2. A 12-gs/s 81-mw 5-bit timeinterleaved flash adc with background timing skew calibration;M El-Chammas;IEEE Journal of Solid-State Circuits,2011
3. An 8 bit 4 gs/s 120 mw cmos adc;H Wei;IEEE Journal of Solid-State Circuits,2014
4. 22.5 a 1.62gs/s time-interleaved sar adc with digital background mismatch calibration achieving interleaving spurs below 70dbfs;L D;2014 IEEE Int. Solid-State Circuits Conf.(ISSCC),2014
5. A 10-bit 2.6-gs/s time-interleaved sar adc with a digital-mixing timing-skew calibration technique;C.-Y Lin;IEEE Journal of Solid-State Circuits,2018