A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-$\mu$m CMOS Technology-Reference-Cited by-同舟云学术

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A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-$\mu$m CMOS Technology

Published:2009-05 Issue:5 Volume:17 Page:688-696
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Min-Sheng Kao ,Jen-Ming Wu ,Chih-Hsing Lin ,Fan-Ta Chen ,Ching-Te Chiu ,Hsu S.S.H.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/4839067/04814487.pdf?arnumber=4814487

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