Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops-Reference-Cited by-同舟云学术

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Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops

Published:2013-04 Issue:4 Volume:21 Page:624-635
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Shyu Ya-Ting,Lin Jai-Ming,Huang Chun-Po,Lin Cheng-Wu,Lin Ying-Zu,Chang Soon-Jyh

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/6481519/06178020.pdf?arnumber=6178020

Cited by 32 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01

2. Key factors in the physical design of high-performance chips;SCIENTIA SINICA Informationis;2024-01-01

3. Power reduction using Unified techniques in Switch-tail Ring counter for sequential circuits;Analog Integrated Circuits and Signal Processing;2023-12-30

4. Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

5. Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05

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