Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling
Author:
Affiliation:
1. Seoul National University,School of Electrical and Computer Engineering,South Korea
Funder
Samsung
Samsung Advanced Institute of Technology
National Research Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10256666/10256705/10256966.pdf?arnumber=10256966
Reference19 articles.
1. Post-placement power optimization with multi-bit flip-flops
2. INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving
3. Effective and efficient approach for power reduction by using multi-bit flip-flops;shyu;TVLSI,2012
4. Clock-gating and its application to low power design of sequential circuits;wu;TCASI Fundamental Theory and Applications,2000
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1. Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible with Commercial EDA Flow;2023 20th International SoC Design Conference (ISOCC);2023-10-25
2. Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips;2023 20th International SoC Design Conference (ISOCC);2023-10-25
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