Post-placement power optimization with multi-bit flip-flops
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/5638200/5648785/05654155.pdf?arnumber=5654155
Cited by 28 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Post-Layout Optimization for Field-coupled Nanotechnologies;Proceedings of the 18th ACM International Symposium on Nanoscale Architectures;2023-12-18
2. Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
3. Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05
4. Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking;ACM Transactions on Design Automation of Electronic Systems;2023-05-17
5. Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization;Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design;2022-10-30
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