An accurate peak and noise model of CTLE applied to the front end of CLKRX
Author:
Affiliation:
1. University of Electronic Science and Technology of China,State Key Lab of Electronic Thin Films and Integrated Devices
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9962815/9963138/09963210.pdf?arnumber=9963210
Reference4 articles.
1. A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector
2. A low-power 10-Gb/s receiver with merged CTLE and DFE summer;liu;2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT),2016
3. A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors
4. Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers
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