Author:
Aghighi Amin,Alameh Abdul Hafiz,Taherzadeh-Sani Mohammad,Nabki Frederic
Cited by
7 articles.
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1. An accurate peak and noise model of CTLE applied to the front end of CLKRX;2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT);2022-10-25
2. A 10-Gbps CTLE design using split-length input pair MOS Transistors;International Journal of Electronics Letters;2022-09-05
3. Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector;VLSI-SoC: Design Trends;2021
4. A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors;2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC);2020-10-05
5. Energy and Area Efficient Mixed-Mode MCMC MIMO Detector;2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC);2020-10-05