Design of a Configurable Digital Phase Locked Loop Circuit-Reference-Cited by-同舟云学术

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Design of a Configurable Digital Phase Locked Loop Circuit

Published:2023-10-27 Issue: Volume: Page:599-602
ISSN:
Container-title:2023 9th Annual International Conference on Network and Information Systems for Computers (ICNISC)
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Author:

Zhou Xudong¹,Ba Can²,Chu Yuan¹,Wang Liang²,Zhang Hao¹

Affiliation:

1. Ningbo Transmission & Transformation Construction Ltd.,Ningbo,China

2. State Grid Zhejiang Electric Power Co., Ltd.,Ningbo Power Supply Company,Ningbo,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10473310/10473311/10473412.pdf?arnumber=10473412

Reference10 articles.

1. Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs

2. A Novel Topology of Coupled Phase-Locked Loops

3. A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise

4. A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 $\mu$m CMOS

5. A Dither-Less All Digital PLL for Cellular Transmitters

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