A Proposed Design of Conventional 4-Bit Carry Look-Ahead Adder Improving Performance
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9210423/9213188/09213227.pdf?arnumber=9213227
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Comparative Study on 4-Bit Adders and Multipliers with Hardware Implementation;2024 7th International Conference on Devices, Circuits and Systems (ICDCS);2024-04-23
2. Hardware Performance Analysis of N-bit CLA on FPGA and Programmable SoC;Proceedings of the 13th International Conference on Advances in Information Technology;2023-12-06
3. Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination;2023 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE);2023-11-08
4. Carry look-ahead and ripple carry method based 4-bit carry generator circuit for implementing wide-word length adder;Microelectronics Journal;2023-10
5. Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator;Engineering Reports;2023-06-29
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