Hardware Performance Analysis of N-bit CLA on FPGA and Programmable SoC-Reference-Cited by-同舟云学术

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Hardware Performance Analysis of N-bit CLA on FPGA and Programmable SoC

Published:2023-12-06 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 13th International Conference on Advances in Information Technology
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Author:

Saha Piyali¹^ORCID,Ghosh Sudip²^ORCID,Pal Debajyoti³^ORCID,Rahaman Hafizur⁴^ORCID

Affiliation:

1. Electronics and Communication Engineering, Seacom Engineering College, India

2. School of VLSI Technology, Indian Institute of Engineering Science and Technology(IIEST), India

3. King Mongkut's University of Technology Thonburi, Thailand

4. Department of Information Technology, Indian Institute of Engineering Science and Technology(IIEST), India

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3628454.3628455

Reference18 articles.

1. A multi-radio unification protocol for IEEE 802.11 wireless networks

2. Designing Carry Look Ahead Adder to Enrich Performance using One Bit Hybrid Full Adder

3. An improved 32-bit carry-lookahead adder with Conditional Carry-Selection

4. Factorized Carry Lookahead Adders

5. Analysis & implementation of ultra low-power 4-bit CLA in subthreshold regime

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