A Low-Power Counter-based Digital CDR
Author:
Affiliation:
1. School of Electrical and Computer Engineering Inha University,Incheon,Republic of Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10031262/10031265/10031478.pdf?arnumber=10031478
Reference4 articles.
1. A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS
2. A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS
3. A Process-Independent and Highly Linear DCO for Crowded Heterogeneous IoT Devices in 65-nm CMOS
4. A 0.42–3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition
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