A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS-Reference-Cited by-同舟云学术

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A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

Published:2021-05 Issue:5 Volume:56 Page:1597-1607
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Park Kwanseo^ORCID,Lee Kwangho^ORCID,Cho Sung-Yong^ORCID,Lee Jinhyung,Hwang Jeongho^ORCID,Choo Min-Seong^ORCID,Jeong Deog-Kyoon^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9411776/09239394.pdf?arnumber=9239394

Cited by 30 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

2. A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06

3. A Wide-Range Reference-Less Digital Clock and Data Recovery for Harmonic-Lock-Free Frequency Acquisition;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

4. A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-03

5. An Anti-Harmonic-Lock Frequency Detector for Continuous-Rate Clock and Data Recovery;2023 20th International SoC Design Conference (ISOCC);2023-10-25

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