A new hybrid multiplieusing Dadda and Wallace method
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6881541/6892507/06892623.pdf?arnumber=6892623
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design and optimization of MSI-enabled multi-precision binary multiplier architecture;i-manager's Journal on Circuits and Systems;2023
2. Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for High-Performance Computing in Memory Architecture;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-11
3. Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication;IET Circuits, Devices & Systems;2021-03-11
4. An Efficient Design of 8 * 8 Wallace Tree Multiplier Using 2 and 3-Bit Adders;Lecture Notes in Networks and Systems;2021
5. High-speed hybrid tree multiplier hardware using modified Wallace and Dadda method;SEVENTH INTERNATIONAL SYMPOSIUM ON NEGATIVE IONS, BEAMS AND SOURCES (NIBS 2020);2021
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