An Efficient Design of 8 * 8 Wallace Tree Multiplier Using 2 and 3-Bit Adders-Reference-Cited by-同舟云学术

An Efficient Design of 8 * 8 Wallace Tree Multiplier Using 2 and 3-Bit Adders

Published:2021 Issue: Volume: Page:23-39
ISSN:2367-3370
Container-title:Lecture Notes in Networks and Systems
language:
Short-container-title:

Author:

Sakthimohan M.,Deny J.

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-33-4355-9_3

Reference15 articles.

1. Wang Y, Li Y, Shen H, Fan D, Wang W, Li L, Liu Q, Zhang F, Wang X, Chang M-F, Liu M (2019) A few-step and low-cost memristor logic based on MIG logic for frequent-off instant-on circuits in IoT applications. IEEE Trans. Circ. Syst. II: Expr. Briefs 66(4)

2. Karuppusamy, P.: Design and analysis of low-power, high-speed Baugh Wooley multiplier. J. Electron. Inf. 01(02), 60–70 (2019)

3. Navin Kumar, M.; Adithyaa, R.S., Bhavan Kumar, D., Pavithra, T.: Design analysis of wallace tree based multiplier using approximate full adder and Kogge stone adder. In: 2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS) (2020)

4. Sundhar, A., Deva Tharshini, S., Priyanka, G., Ragul, S., Saranya, C.: Performance analysis of Wallace tree multiplier with Kogge stone adder using 15–4 compressor. In: 2019 International Conference on Communication and Signal Processing (ICCSP) (2019)

5. Mukherjee, B., Ghosal, A.: Counter based low power, low latency Wallace tree multiplier using GDI technique for on-chip digital filter applications. IEEE Conf. EC-13, 14–17 (2019)

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Automated Class Intimation System for Educational Institutions using Artificial Neural Networks;2024 3rd International Conference on Applied Artificial Intelligence and Computing (ICAAIC);2024-06-05

2. Automated and Interactive Smart Bin Implementation in Urban Zones;2024 Third International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS);2024-03-14

3. Area Efficient and Ultra Low Power Full Adder Design Based on GDI Technique for Computing Systems;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2024

4. An Optimized 4*4 Braun Multiplier for Parallel Processing Architectures with a 3-bit KSA Adder;2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM);2023-12-18

5. Deep Learning-Powered Face Recognition Attendance System: A Novel Approach to Automated Prediction;2023 2nd International Conference on Automation, Computing and Renewable Systems (ICACRS);2023-12-11