Design of low-leakage and high writable proposed SRAM cell structure
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6881541/6892507/06892682.pdf?arnumber=6892682
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Design and Implementation of CNFET SRAM Cells by Using Multi-Threshold Technique;Electronics;2023-03-29
2. Design of a Highly Reliable Low Power Stacked Inverter-Based SRAM Cell with Advanced Self-recoverability from Soft Errors;Advances in Cognitive Science and Communications;2023
3. A variation-aware design for storage cells using Schottky-barrier-type GNRFETs;Journal of Computational Electronics;2020-06-12
4. Performance evaluation of double gate tunnel FET based chain of inverters and 6-T SRAM cell;Engineering Research Express;2019-12-18
5. A novel charge recycle read write assist technique for energy efficient and fast 20 nm 8T-SRAM array;Solid-State Electronics;2018-10
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