Design of a Highly Reliable Low Power Stacked Inverter-Based SRAM Cell with Advanced Self-recoverability from Soft Errors
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-8086-2_40
Reference14 articles.
1. Ebara M, Yamada K, Kojima K et al (2019) Process dependence of soft errors induced by α particles, heavy ions, and high energy neutrons on flip flops in FDSOI. IEEE J Electron Devices Soc 7(1):817–824
2. Nayak D, Acharya DP, Rout PK, Mahapatra KK (2014) Design of low-leakage and high writable proposed SRAM cell structure. In: International conference on electronics and communication systems (ICECS), Coimbatore, 2014, pp 1–5
3. Cai S, Wang W, Yu F et al (2019) Single event transient propagation probabilities analysis for nanometer CMOS circuits. J Electron Test Theory Appl 35(2):163–172
4. Upadhyay P, Mandal A, Kar R, Mandal D, Ghoshal SP (2018) A low power 9T SRAM cell design for both active and passive mode. In: 15th International conference on electrical engineering/electronics, computer, telecommunications and information technology (ECTI-CON), Chiang Rai, Thailand, 2018, pp 672–675
5. Narasimham B, Gupta S, Reed D, et al (2018) Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs. IntReliab Phys Symp 1–4
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