Fault emulation: A new methodology for fault grading-Reference-Cited by-同舟云学术

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Fault emulation: A new methodology for fault grading

Published:1999 Issue:10 Volume:18 Page:1487-1495
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Kwang-Ting Cheng ,Shi-Yu Huang ,Wei-Jin Dai

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/17165/00790625.pdf?arnumber=790625

Cited by 49 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Stuck at Fault Testing in Combinational Circuits Using FPGA;Proceedings of Emerging Trends and Technologies on Intelligent Systems;2021-10-02

2. Information Leakage Analysis using a Co-design-Based Fault Injection Technique on a RISC-V Microprocessor;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021

3. An online fault injection method for the dynamic partial reconfiguration system based on a lightweight ICAP controller;IEICE Electronics Express;2018

4. An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs;Microelectronics Reliability;2017-08

5. Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-06

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