Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms
Author:
Affiliation:
1. Peking University,Beijing,China
2. Nano Core Chip Electronic Technology,Hangzhou,China
Funder
National Key R&D Program of China
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731573.pdf?arnumber=9731573
Reference13 articles.
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2. 28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications
3. A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit
4. A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment
5. A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless loT Sensor Nodes;gupta;IEEE Symp VLSI Circuits,0
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