A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit-Reference-Cited by-同舟云学术

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A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit

Published:2013-02 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
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Author:

Tachibana F.,Hirabayashi O.,Takeyama Y.,Shizuno M.,Kawasumi A.,Kushida K.,Suzuki A.,Niki Y.,Sasaki S.,Yabe T.,Unekawa Y.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6480926/6487590/06487752.pdf?arnumber=6487752

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms;2022 IEEE International Solid- State Circuits Conference (ISSCC);2022-02-20

2. Adaptive Time-based Encoding for Energy-Efficient Large Cache Architectures;Proceedings of the 5th International Workshop on Energy Efficient Supercomputing;2017-11-12

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