A Multichannel Serial Link Receiver With Dual-Loop Clock-and-Data Recovery and Channel Equalization
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/6646285/06509474.pdf?arnumber=6509474
Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Fractionally-Spaced Equalizers as Clock and Data Recovery Loops;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-07
2. A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR;IEICE Electronics Express;2023-05-25
3. Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization;IEEE Open Journal of Circuits and Systems;2023
4. A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-10
5. A 12.5 Gbps clock and data recovery circuit with phase interpolation based digital locked loop;IEICE Electronics Express;2020-10-25
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