47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

Author:

Saito Mitsuko,Yoshida Yoichi,Miura Noriyuki,Ishikuro Hiroki,Kuroda Tadahiro

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of SRAM Based Interface Module with DMA in Inductive-Coupling 3D Stacked IoT Chips;2022 2nd International Conference on Intelligent Technology and Embedded Systems (ICITES);2022-09-23

2. Ferrite-Less Frequency-Tuned Printed-Coil Resonator With Rear Metallic Plate for RFID Applications;IEEE Journal of Radio Frequency Identification;2021-03

3. A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-02

4. 3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface;2017 14th International Symposium on Pervasive Systems, Algorithms and Networks & 2017 11th International Conference on Frontier of Computer Science and Technology & 2017 Third International Symposium of Creative Computing (ISPAN-FCST-ISCC);2017-06

5. A simultaneously bidirectional inductively coupled link in a 0.13-µm CMOS technology;International Journal of Circuit Theory and Applications;2016-07-05

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