Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/5934463/05893958.pdf?arnumber=5893958
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analysis and Design of a Low-Voltage Low-Power High SNDR Current-Mode Sample and Hold Circuit Based on CMOS Technology;Wireless Personal Communications;2024-07
2. A Wide-Band High-Speed Sample and Hold in 0.35µm CMOS Technology;2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS);2023-02-27
3. Gain-Boosted Super Class AB OTAs Based on Nested Local Feedback;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-09
4. A Compact Sub-μW CMOS ECG Amplifier With 57.5-MΩ Zin, 2.02 NEF, 8.16 PEF and 83.24-dB CMRR;IEEE Transactions on Biomedical Circuits and Systems;2021-06
5. An energy-efficient sample-and-hold circuit in CNTFET technology for high-speed applications;Analog Integrated Circuits and Signal Processing;2020-03-02
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