A Wide-Band High-Speed Sample and Hold in 0.35µm CMOS Technology
Author:
Affiliation:
1. Univ. Bordeaux,Bordeaux INP, UMR CNRS 5218, IMS Laboratory,Talence,France,33405
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10108078/10108098/10108219.pdf?arnumber=10108219
Reference8 articles.
1. Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit
2. Low-Distortion Correlated Level Shifting Sample-and-Hold Stage
3. Low-Voltage CMOS Analog Bootstrapped Switch For Sample-and-Hold Circuit: Design and Chip Characterization
4. Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit
5. A high performance class AB CMOS rail to rail voltage follower
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1. Analysis and Design of a Low-Voltage Low-Power High SNDR Current-Mode Sample and Hold Circuit Based on CMOS Technology;Wireless Personal Communications;2024-07
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