An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/6125259/05954144.pdf?arnumber=5954144
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1. Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure;2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD);2023-07-03
2. Process Variability-Aware Analytical Modeling of Delay in Subthreshold Regime with Device Stacking Effects;Communications in Computer and Information Science;2021
3. Process‐induced variability modeling of subthreshold leakage power considering device stacking;International Journal of Circuit Theory and Applications;2020-02-06
4. A Simple General-purpose I-V Model for All Operating Modes of Deep Submicron MOSFETs;International Journal of Engineering;2018-02
5. Impact analysis of statistical variability on the accuracy of a propagation delay time compact model in nano-CMOS technology;Journal of Computational Electronics;2017-12-04
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