Process‐induced variability modeling of subthreshold leakage power considering device stacking-Reference-Cited by-同舟云学术

Process‐induced variability modeling of subthreshold leakage power considering device stacking

Published:2020-02-06 Issue:5 Volume:48 Page:739-749
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int J Circ Theor Appl

Author:

Reddy Anala M.¹^ORCID,Harish B.P.²

Affiliation:

1. Department of Electronics and Communication Engineering, University Visvesvaraya College of EngineeringBangalore University Bangalore India

2. Department of Electrical Engineering, University Visvesvaraya College of EngineeringBangalore University Bangalore India

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/cta.2755

Reference26 articles.

1. ChangH SapatnekarSS.Full‐chip analysis of leakage power under process variations including spatial correlations. In: Proc. Design Autom. Conf.;CA USA:523‐528.

2. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

3. Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile

4. ChauR DattaS DoczyM KavalierosJ MetzM.Gate dielectric scaling for high‐performance CMOS: from SiO2 to High‐K. In: Proc. Extended Abstracts Int. Workshop Gate Insulator;2003;Tokyo Japan:124‐126.

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