Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells-Reference-Cited by-同舟云学术

Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells

Published:2022-12-03 Issue: Volume: Page:
ISSN:
Container-title:2022 International Electron Devices Meeting (IEDM)
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Author:

Vega-Gonzalez V.¹,Radisic D.¹,Choudhury S.¹,Tierno D.¹,Thiam A.¹,Batuk D.¹,Martinez G.T.¹,Seidel F.¹,Decoster S.¹,Kundu S.¹,Tsvetanova D.¹,Peter A.¹,De Coster H.¹,Sepulveda-Marquez A.¹,Altamirano-Sanchez E.¹,Chan Bt¹,Drissi Y.¹,Sherazi Y.¹,Uk-Lee J.¹,Ciofi I.¹,Murdoch G.¹,Nagesh N.¹,Hellings G.¹,Ryckaert J.¹,Biesemans S.¹,Litta E. Dentoni¹,Horiguchi N.¹,Park S.¹,Tokei Zs.¹

Affiliation:

1. imec vzw Kapeldreef 75 B-3001,Leuven,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10019319/10019320/10019483.pdf?arnumber=10019483

Reference9 articles.

1. Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

2. Novel forksheet device architecture as ultimate logic scaling device towards 2nm

3. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

4. Plasma etch selectivity study and material screening for self-aligned gate contact (SAGC)

5. Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm

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