41% Reduction In Power Stage Area On Silicon-On-Insulator Bipolar-CMOS-DMOS-IGBT Platform With Newly Developed Multiple Deep-Oxide Trench Technology-Reference-Cited by-同舟云学术

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41% Reduction In Power Stage Area On Silicon-On-Insulator Bipolar-CMOS-DMOS-IGBT Platform With Newly Developed Multiple Deep-Oxide Trench Technology

Published:2022-12-03 Issue: Volume: Page:
ISSN:
Container-title:2022 International Electron Devices Meeting (IEDM)
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Author:

Zhang Long¹,Ma Jie¹,Gu Yong¹,Liu Siyang¹,Wei Jiaxing¹,Li Sheng¹,Sun Weifeng¹,Zhang Sen²

Affiliation:

1. Southeast University,National ASIC System Engineering Research Center,Nanjing,China

2. CSMC Technologies Corporation,Wuxi,China.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10019319/10019320/10019416.pdf?arnumber=10019416

Reference9 articles.

1. On the Investigation of the “Anode Side” SuperJunction IGBT Design Concept

2. A Carrier Stored SOI LIGBT With Ultralow ON-State Voltage and High Current Capability

3. 650 V Super-Junction Insulated Gate Bipolar Transistor Based on 45 μm Ultrathin Wafer Technology

4. A Superjunction U-MOSFET With SIPOS Pillar Breaking Superjunction Silicon Limit by TCAD Simulation Study

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor: Current Technologies and Prospects;IEEE Transactions on Electron Devices;2024-01

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