Author:
Sengupta Suchismita,Sarkar Partha,Dastidar Ananya
Cited by
4 articles.
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1. Development of Power-Delay Product Optimized ASIC-Based Computational Unit for Medical Image Compression;Technologies;2024-07-29
2. A 2.319 uW, 37.34 MHz Transmission Gate Based 4-Bit ALU for Contemporary Low-powered, High-Speed Microprocessors;2024 6th International Conference on Electrical Engineering and Information & Communication Technology (ICEEICT);2024-05-02
3. Design and Implementation of ALU Using Ring Counters;2023 International Conference on Signal Processing, Computation, Electronics, Power and Telecommunication (IConSCEPT);2023-05-25
4. Design of a Low-power Computational Unit using a Pipelined Vedic Multiplier;2023 International Conference for Advancement in Technology (ICONAT);2023-01-24