Design of a Low-power Computational Unit using a Pipelined Vedic Multiplier-Reference-Cited by-同舟云学术

Design of a Low-power Computational Unit using a Pipelined Vedic Multiplier

Published:2023-01-24 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference for Advancement in Technology (ICONAT)
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Author:

Mendez Tanya¹,Nayak Subramanya G.¹

Affiliation:

1. Manipal Institute of Technology,Manipal Academy of Higher Education,Department of Electronics and Communication Engineering,Manipal,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10079844/10079947/10080520.pdf?arnumber=10080520

Reference19 articles.

1. Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow;buzdar;International Journal of Advanced Computer Science and Applications,2016

2. Design and analysis of competent arithmetic and logic unit for RISC processor;priyanka;ARPN Journal of Engineering and Applied Sciences,2016

3. Implementation of Low Leakage and High Performance 8-Bit ALU for Low Power Digital Circuits;akram;International Journal of Computer Applications (0975 – 8887),2013

4. Power Optimization of Sequential Circuit Based ALU Using Gated Clock & Pulse Enable Logic

5. A 180 nm efficient low power and optimized area ALU design using gate diffusion input technique

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3. Design and Implementation of RISC-V Based Pipelined Multiplier;Journal of Physics: Conference Series;2023-10-01