Design and Implementation of RISC-V Based Pipelined Multiplier

Abstract

Abstract Among the many microprocessors, RISC-V as an open-source instruction set is gradually gaining popularity among academia and industry. The performance of the multiplier in the microprocessor imposes constraints on the computational power of the processor. In order to improve the efficiency of multiplication instructions, a pipeline multiplier is implemented in this paper. Firstly, the partial product is generated using the Radix-4 booth. Secondly, the Wallace tree structure is used to accelerate the compression of the partial product. Then, a parallel prefix adder is used to calculate the resulting partial product to improve the timing. Finally, registers are added as a pipeline to achieve a high-efficiency multiplication calculation. With the operating voltage and temperature set to typical conditions, the integrated multiplier area is 50260.6 μm2, and the power consumption is 20.41 mW. The final frequency of the multiplier is 1 GHz in gate-level simulation.