A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DAC-Reference-Cited by-同舟云学术

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A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DAC

Published:2018-06 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE Symposium on VLSI Circuits
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Author:

Chen Haiwen,Zhot Xiong,Yu Qiang,Zhang Fan,Li Qiang

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8484863/8502213/08502370.pdf?arnumber=8502370

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Algorithm-Hardware Co-Design for Energy-Efficient A/D Conversion in ReRAM-Based Accelerators;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

2. A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage;IEEE Journal of Solid-State Circuits;2024

3. An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-11

4. MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

5. ES-MPQ: Evolutionary Search Enabled Mixed Precision Quantization Framework for Computing-in-Memory;2023 IEEE 12th Non-Volatile Memory Systems and Applications Symposium (NVMSA);2023-08

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