A Dual PFD Phase Rotating Multi-Phase PLL for 5Gbps PCI Express Gen2 Multi-Lane Serial Link Receiver in 0.13um CMOS-Reference-Cited by-同舟云学术

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A Dual PFD Phase Rotating Multi-Phase PLL for 5Gbps PCI Express Gen2 Multi-Lane Serial Link Receiver in 0.13um CMOS

Published:2007-06 Issue: Volume: Page:
ISSN:
Container-title:2007 IEEE Symposium on VLSI Circuits
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Author:

Kim Sungjoon,Lee Dongyun,Park Young-Soo,Moon Yongsam,Shim Daeyun

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4342660/4342661/04342732.pdf?arnumber=4342732

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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