A 6-Gbps/lane receiver for a clock-forwarded link in 65-nm CMOS process

Author:

Ahn Keun-Seon1,Yoo Changsik1

Affiliation:

1. Integrated Circuits Laboratory, Department of Electronic Engineering; Hanyang University; Seoul 133-791 Republic of Korea

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference15 articles.

1. Choi H Kim G Shim D Kim B Hwang SH Reduced dead-cycle, adaptive phase tracking method and apparatus 7,236,553 2007

2. Luo Y-B Chen P Chen Q-T Wang C-Y Chang C-H Fu S-J Chen C-M Li H-S A 250 Mb/s-to-3.4Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer Digest of Technical Papers, IEEE International Solid-State Circuits Conference San Francisco, USA 2009 190 191

3. Kim S Lee D Park Y-S Moon Y Shim D A dual-PFD phase rotating multi-phase PLL for 5Gbps PCI express Gen2 multi-lane serial link receiver in 0.13 µm CMOS Digest of Technical Papers, IEEE VLSI Circuits Symposium Kyoto, Japan 2007 234 235

4. A 0.6 mW/Gb/s 6.4-7.2Gb/s serial link receiver using local injection locked ring oscillators in 90 nm CMOS;Hu;IEEE Journal of Solid-State Circuits,2010

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1. Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation;International Journal of Circuit Theory and Applications;2018-07-23

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