A 5-Gbit/s CDR circuit with 1.4 mW multi-PFD phase rotating PLL
Author:
Affiliation:
1. Memory Division, Samsung Electronics Co.
2. College of Information & Communication Engineering, Sungkyunkwan University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/11/24/11_11.20140828/_pdf
Reference11 articles.
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2. [2] P. K. Hanumolu, G.-Y. Wei and U.-K. Moon: IEEE J. Solid-State Circuits 43 (2008) 425. DOI:10.1109/JSSC.2007.914290
3. [3] T. Toifl, C. Menolfi, P. Buchmann, M. Kossel, T. Morf, R. Reutemann, M. Ruegg, M. L. Schmatz and J. Weiss: IEEE J. Solid-State Circuits 40 (2005) 2700. DOI:10.1109/JSSC.2005.856581
4. [4] J. Poulton, R. Palmer, A. M. Fuller, T. Greer, J. Eyles, W. J. Dally and M. Horowitz: IEEE J. Solid-State Circuits 42 (2007) 2745. DOI:10.1109/JSSC.2007.908692
5. [5] S. Kim, D. Lee, Y.-S. Park, Y. Moon and D. Shim: Symp. VLSI Circuits Dig. Tech. (2007) 234. DOI:10.1109/VLSIC.2007.4342732
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