A 0.6V 45nm adaptive dual-rail SRAM compiler circuit design for lower VDD_min VLSIs
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4573021/4585928/04586010.pdf?arnumber=4586010
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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