Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption
Author:
Affiliation:
1. Chuo University
2. Nihon University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E106.C/9/E106.C_2022ECP5053/_pdf
Reference13 articles.
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3. [3] K. Zhang, U. Bhattacharya, C. Zhanping, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply,” IEEE J. Solid-State Circuits, vol.41, no.1, pp.146-151, Jan. 2006. 10.1109/jssc.2005.859025
4. [4] O. Hirabayashi, A. Kawasumi, A. Suzuki, Y. Takeyama, K. Kushida, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, T. Nakazato, Y. Shizuki, N. Kushiyama, and T. Yabe, “A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 cell in 40nm CMOS using level-programmable wordline driver,” Digest of Technical Papers, International Solid-State Circuits Conference, pp.458-459, Feb. 2009. 10.1109/isscc.2009.4977506
5. [5] S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, T. Yoshihara, M. Igarashi, M. Takeuchi, H. Kawashima, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi, and H. Shinohara, “A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability with Read and Write Operation Stabilizing Circuits,” IEEE J. Solid-State Circuits, vol.42, no.4, pp.820-829, April 2007. 10.1109/jssc.2007.891648
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